Design Lab · experimental
State a digital-design requirement. The lab generates the HDL, runs it through an open-source simulator, and draws the circuit — automatically, on free CI.
Worked examples
The classic sequential-plus-concurrent FSM: four timed states (hot / drain / cold / drain), level-sensor transitions, built from D/T flip-flops, pulse generators and down-counters. Real VHDL → simulated → drawn.
A plain-English requirement → Gemini-generated Verilog → simulated on Icarus → drawn by Yosys. The sequence 00 → 01 → 11 → 10 with a synchronous reset — generated, checked and rendered end-to-end.
Run the harness above with any requirement — a UART, an ALU, a traffic-light controller — and it lands here once the build finishes.